Intel pledges 80 cores in five years

From TomsHardware:

Intel has built a prototype of a processor with 80 cores that can perform a trillion floating point operations per second.

CPUs are accelerating their gain of processing power and, in the near future, Intel believes that a single chip could perform a trillion instructions per second and replace dozens of servers. At the IDF, the firm gave a sneak peek of an upcoming 80-core processor for the "mega data-center."

Using a combination of 80-CPU cores, directly-bonded cache memory and on-die lasers, the chip can push to 1 Teraflops, or a trillion floating point instructions per second, and has an external bandwidth of 1 Terabit per second. In comparison, today's Core 2 Duo processors are estimated to reach a performance of about 25 GFlops.

According to chief technology officer Justin Rattner, the cores on the new 3.1 GHz chip are not full CPU cores, but floating point accelerators, comparable to the to cores in the IBM Cell or Sun Microsystem's Niagara processor. Rattner said the prototype chip could reach the market in about five years.

Each core on the chip will have 256 Mb of directly bonded static RAM cache. The memory has been attached to the bottom of the processor and is the key component in providing an aggregate memory bandwidth of 1 Tb per second.

How will the laser chips communicate with the motherboard and other processors? A multiplexor will combine the light into a single fiber optic link with 1 terabit per second bandwidth. Rattner says this is a 50X increase over the best electrical link.

But all of this processing power is rather useless if you can't get the information around to different cores and outside of the chip, so Rattner brought in John Bowers a University of California Santa Barbara professor to explain how hybrid lasers will help I/O speeds.

Intel and UCSB have been partnering up on laser research for several years. Lasers are well known for their gigantic data transmission rates as evidenced in fiber optic cables, but you couldn't put those cables on computer chips, until now. Using CMOS manufacturing techniques, Intel and UCSB etched tiny tunnels or wave guides onto chips. Then a layer of indium-phospide was stacked on top. Light is produced and travels down the wave guide when electrical current is applied to the layers.

Bowers explained that traditional expenses for lasers have been high, but Intel's method is much cheaper because it uses the same manufacturing facilities.

So far Intel has been able to pack 25 lasers onto thin bars and 1000 lasers onto square chips. Bowers and Rattner gave what they say is the world's first onstage demonstration of a hybrid laser. Attendees gawked at monitors which showed the beam end of a prototype four-laser chip. The beams momentarily disappeared off the screens after Rattner placed his hotel keycard into the path.

The new chip will have at least 25 lasers which will be multiplexed into a single fiber optic outbound link with 1 TB/s bandwidth. Rattner said this was a 50 times increase in bandwidth over comparable electrical links and added that "hundreds of wires" were being eliminated.